Double or multiple exposures are used in semiconductor fabrication to allow the formation of integrated circuits with particularly high integration densities. One reason for the use of double or multiple exposures (also referred to below just as double exposure) is, for example, the different imaging properties of projection optics between dense, periodic arrangements of structures on the one hand and isolated structures on the other hand.
Fault-free, ideal lenses of projection optics lead to decreases in the size of process windows for lithographic projection onto semiconductor wafers in the case of both isolated and dense, periodic arrangements being present together within a single structure pattern. If the standard distortions of the lenses, known as the aberrations, are also factored in, there is a further deterioration in the process window.
The different structure arrangements could in each case be imaged in optimized form by individually adjusted exposure arrangements. Therefore, since common projection of different arrangements of structures within a pattern can only be imaged using a common projection step, the tendency is for the combined patterns to be separated into the respective arrangements with differing requirements and for these separated arrangements then to be projected onto the wafer in different exposure operations, i.e., the double exposures.
Another reason for carrying out double exposures is, for example, the separation of structures with a high degree of resolution and a very small feature size from structures which have lower demands imposed on the resolution. If, on the one hand, there are certain conditions relating to the arrangement of the structures which are to have a high degree of resolution, such as, for example, row-column patterns with a row-to-column ratio of 1:1, alternating phase masks can be used for this purpose, whereas inexpensive masks with a low resolution suffice for the surrounding, large-area structures.
Accordingly, double exposures require mask sets in which one mask accommodates a part of the structure pattern, which is to be formed together in the resist, and subsequently in the level below. The corresponding structure pattern parts, also referred to below simply as structure patterns, have a relatively high degree of positional accuracy with respect to one another, in order, for example, to allow electrical connection of interconnects which are to be formed. Therefore, it is also necessary to allow very accurate alignment of the corresponding masks in the successive exposure process.
One typical double exposure process is illustrated in FIG. 1. The left-hand side shows an actual projection system. The projection system includes a radiation source 5, a first mask substrate holder 30 with a first mask 4 fit in the holder 30, a lens, which represents the projection optics 6, and a wafer 8, which has been placed on a substrate holder 9. This example in accordance with the prior art is a wafer stepper or scanner. In a size-reducing imaging step (reduction optics), a first structure pattern 51 which has been applied to the mask 4 is transferred in steps into one exposure field 60 on the wafer 8. The first structure pattern 51 may be a number of chip levels, for example, word line levels (gate conductor levels) of a number of DRAM memory chips.
The double exposure is carried out by the first mask 4 having the first structure pattern 51 being regularly exchanged with a second mask 6 with a second structure pattern 52 arranged thereon by the handling units 40, 42. The second mask 6 is initially located in a second mask substrate holder 34 in a parked or loading position.
When a production batch of, for example, 25 wafers reaches an exposure apparatus, such as, for example, a wafer stepper or scanner, for exposure, the masks 4, 6 for the double exposure are removed from a mask store 14 in the exposure apparatus and fed to the second mask holder 34 on a transport path 22 by a transport system 20 in accordance with a manufacturing command. The second mask holder 34 also serves as a pre-loading station for the masks, from which the handling appliances 40, 42 feed the relevant mask into the first mask substrate holder 30, which is used for exposure. However, before the masks 4, 6 are fed to the exposure, it is customary for the bar code on the mask also to be checked in a bar code-reading station 16. Furthermore, in a testing appliance 18, the pellicle, which is generally mounted on masks, is checked for the presence of any particle contamination.
If the relevant masks 4, 6 are not yet even in the exposure apparatus, the masks may also be loaded into the exposure apparatus externally via mask-loading stations 10, 12.
Once the first mask 4 has been placed into the mask substrate holder 30 by the handling appliance 40, the mask 4 first has to be aligned. For this purpose, 16 alignment parameters first have to be loaded. This is followed by the exposure sequence, according to which the exposure fields of the wafer in succession are first exposed using the structure pattern 51 of the first mask 4. Then, the first mask 4 is unloaded by the second handling appliance 42, while in the meantime the first handling appliance 40 unloads the second mask 6 from the second mask holder 34 and places it into the first mask holder 30, which is now free. After this exchange of masks, further alignment with redetermination of the 16 parameters is required. The changeover times for the two masks are typically between 15 and 30 seconds. Two seconds are required for each realignment. After the exposure fields on a first wafer 8 have been completed, a second wafer can then be loaded and exposed starting with the second structure pattern 52 of the second mask 6. This is once again followed by the exchange of masks and the realignment.
In addition to the obvious loss of time caused by the exchange path through the handling appliances 40, 42 and in each case the realignment, a loss of quality in particular on account of the large number of realignments also plays a certain role in assessing the result on the wafer 8. Typical stipulated tolerances for the positional accuracy within a layer level are currently from 10 to 13 nm. Differences in the positional displacements caused by different exposure settings must not exceed 7 to 10 nm. Therefore, additional alignment errors caused by realignment operations having to be carried out should be kept to a minimum, since such errors are in addition to the apparatus-dependent errors.
To improve the quality of the double or multiple exposure process is desirable. Moreover, to increase the throughput involved in the production of integrated circuits requiring double or multiple exposure is also desirable.